Design and implementation of a neural network in an FPGA for pattern recovery

Authors

  • Aurelio Morales Villanueva Faculty of Electrical and Electronic Engineering, National University of Engineering, Lima, Perú. https://orcid.org/0000-0002-5469-4912
  • Cesar Briceño Aranda Faculty of Electrical and Electronic Engineering, National University of Engineering, Lima, Perú.

DOI:

https://doi.org/10.21754/tecnia.v17i2.367

Keywords:

neural network, FPGA, pattern retrieval

Abstract

This research work shows the design and implementation in hardware based on highly complex programmable logic devices such as FPGAs, of a Hopfield artificial neural network for the recovery of stored patterns from fuzzy patterns. They were designed in artificial neural networks (basic and advanced), using FDA electronic design tools and hardware description language.

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References

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[12] McEliece, R., Posner, E., Rodemich, E., Venkatesh, S., "The Capacity of the Hopfield Associative Memory" IEEE Trans. Information Theory IT-33(4) pp. 461-482, USA, 1987.

[13] Morales, A., Briceño, C., "Diseño e implementación de una red neuronal en un FPGA para recuperación de patrones" Informe Final, Instituto de Investigación FIEE-UNI, Lima - Perú, 2008.

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Published

2007-12-01

How to Cite

[1]
A. Morales Villanueva and C. Briceño Aranda, “Design and implementation of a neural network in an FPGA for pattern recovery”, TEC, vol. 17, no. 2, pp. 1–12, Dec. 2007.

Issue

Vol. 17 No. 2 (2007)

Section

Computing and Computer Science

License

Copyright (c) 2007 TECNIA

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